Industries · Semiconductor & EDA

Move design and verification data across every fab and site.

Chip design runs on massive EDA simulation, regression, and verification data, plus tape-out files that move between design centers and fabs across the US, Europe, and Taiwan. Zettar moves it at line rate over any distance, fills even national-scale research and private networks, keeps IP encrypted and provably intact, and feeds HPC verification clusters without the wait.

Who we serveChip design / EDAVerificationTape-outFoundries / fabs
The problem

Design data outgrows the window you have to move it.

  • EDA regression and verification datasets outgrow your transfer window.
  • Design data and tape-out files crawl between US / EU / Taiwan sites over long distances.
  • IP in transit must be encrypted and provably intact.
  • HPC verification and simulation clusters stall waiting on data.
How Zettar helps

Line rate between every design center and fab.

Global by design

Any site, any distance

Distance-insensitive — validated over real 5,000- and 12,375-mile transfers. Zettar moves design and tape-out data site-to-site at line rate, so US, EU, and Taiwan teams work from the same data without the wait.

Scale-out

Fills national-scale pipes

Linear scale-out with no software ceiling. Where the network is huge — up to 1.6 Tbps, as on Taiwan's research networks — Zettar fills it. Your infrastructure is the limit, and Zettar reaches it.

IP-safe

Encrypted & provably intact

Encrypted with TLS and unconditional end-to-end checksums on every transfer. Your IP moves between sites protected in flight and proven bit-for-bit identical on arrival.

Feeds HPC

Clusters stay fed

Scale-out file and object movement that keeps verification and simulation clusters fed instead of idle. Turnkey and platform-neutral — runs on the hardware and networks you already have.

Proof, not promises
"Zettar moved an actual petabyte over a 5,000-mile network loop in 29 hours — encrypted and checksummed — at 96% bandwidth utilization."
— SLAC National Accelerator Laboratory & ESnet, U.S. DOE Read the record → See the paper →

That run was capped at 80 Gbps to spare the shared network — on a full 100 Gbps link, it's a petabyte a day.

1.6 Tbps
fills even national-scale networks — where the network provides it
Build your business case

Put a number on it — and make your case.

FAQ

Common questions

FAQ

How does Zettar move EDA and verification data faster?

At line rate, scaling out with no software ceiling — it fills whatever bandwidth your sites and HPC clusters have, roughly 10x typical movers, so verification is not waiting on data.

FAQ

Can it move design data between global sites and fabs?

Yes — zx is distance-insensitive, validated over real 5,000- and 12,375-mile transfers, so design centers and fabs across the US, Europe, and Taiwan move data at full speed.

FAQ

How large a network can it fill?

There is no software ceiling. Where the network is huge — up to 1.6 Tbps, as on Taiwan's research networks — zx scales out to fill it; the limit is your infrastructure, not the mover.

FAQ

Is IP protected in transit?

Every transfer is encrypted with TLS and protected by unconditional end-to-end checksums — provably intact, never silently altered.

FAQ

Does it feed HPC verification clusters?

Yes — scale-out file and object movement keeps simulation and verification clusters fed, on the servers you already run or a turnkey appliance.

Get started

Keep every fab and design center on the same data.

See the zx Appliance move EDA, verification, and tape-out data at line rate — across any distance, encrypted and provably intact.